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general description the max1620/max1621 convert a 1.8v to 20v battery voltage to a positive or negative lcd backplane bias voltage. backplane bias voltage can be automatically disabled when the display logic voltage is removed, protecting the display. these devices use very little pc board area, come in ultra-small qsop packages, and require only small, low-profile external components. output voltage can be set to a desired positive or nega- tive voltage range with external resistors, and adjusted over that range with the on-board digital-to-analog con- verter (dac) or with a potentiometer. the max1620/ max1621 include a 5-bit dac, allowing digital software control of the bias voltage. the max1620 uses up/down digital signaling to adjust the dac, and the max1621 uses the system management bus (smbus) 2-wire serial interface. these devices use a low-cost, external, n-channel mosfet power switch or npn transistor, and can be configured for positive or negative output voltages. operating cur- rent is a low 150?, typically provided from a display? logic supply of 3.0v to 5.5v. the max1620/max1621 are available in a 16-pin qsop package. applications notebook computers palmtop computers personal digital assistants portable data-collection terminals features ? 1.8v to 20v battery input voltage ? automatic disable when display logic is shut down ? extremely small qsop package ? 32-level internal dac ? smbus serial interface (max1621) ? positive or negative output voltage max1620/max1621 digitally adjustable lcd bias supplies ________________________________________________________________ maxim integrated products 1 part max1620 eee max1621 eee -40? to +85? -40? to +85? temp. range pin-package 16 qsop 16 qsop evaluation kit manual follows data sheet ordering information 19-1214; rev 1; 1/98 lx dhi dlo pgnd dout fb v dd pol shdn dn up ref agnd max1620 12.5v to 23.5v out 2v to 12v 3v to 5.5v on / off down up lcdon pok batt typical operating circuit smbus is a trademark of intel corp. pin configuration 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 dhi dlo lx pgnd agnd v dd dout fb dn (sda) up (scl) batt shdn (sus) pok ref pol lcdon top view max1620 max1621 qsop ( ) are for max1621 only. 8 for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
max1620/max1621 digitally adjustable lcd bias supplies 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.3v, v batt = 10v, t a = 0? to +85? , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd ..............................................................-0.3v to 6v pgnd to agnd ..................................................................?.3v batt, lx, lcdon to agnd ....................................-0.3v to 30v dhi, dlo to pgnd.....................................-0.3v to (v dd + 0.3v) dout, fb, pol, pok, ref to agnd.........-0.3v to (v dd + 0.3v) up, dn, shdn to agnd.............................................-0.3v to 6v scl, sda, sus to agnd............................................-0.3v to 6v i dhi ......................................................................................60ma i dlo ....................................................................................-30ma i lcdon ...............................................................................-10ma continuous power dissipation (t a = +70?) qsop (derate 8.3mw/? above +70?) ......................667mw operating temperature range max1620eee/max1621eee ............................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? v lcdon = 28v, pok = 0.967v v lcdon = 0.4v, pok = 1.017v fb = -50mv fb = ref + 100mv pol = agnd, 3.0v v dd 5.5v shutdown mode, v shdn = v dd ,v dd = 5.5v pol = v dd , 3.0v v dd 5.5v operating mode, output in regulation, v dd = 5.5v v dd = 5v v dd = 5v v dd = 3.0v lx = 12v, shutdown mode v dd = 4.5v lx = 12v, operating mode batt = 12v, shutdown mode 4v batt 12v, t a = 0? to +85? batt = 12v, operating mode 1.8v batt 20v, t a = +25? ? 1 lcdon high, leakage current ma -2 -6 lcdon low, sinking current na -10 85 -20 10 fb input current (note 3) mv -8 0 8 v 1.46 1.5 1.53 fb regulation voltage ma -25 dlo output current (note 3) ma 50 dhi output current (note 3) 14 7 on-resistance (dlo, dhi) 16.5 23.5 ?-v 20 microsecond-volt time constant (k-factor) v 27 positive output voltage 920 ? 150 250 v dd supply current 1.8 20 batt operating range (note 2) 1 ? 13 20 lx input current ? 1 batt input current -27 negative output voltage v 1.5 2.8 undervoltage lockout threshold (note 1) 13 20 v 3.0 5.5 v dd operating range voltage on pok rising v 0.967 0.992 1.017 pok threshold voltage v mv 12 pok hysteresis conditions units min typ max parameter v no load v 1.47 1.5 1.53 ref voltage 0? i ref 25ma mv 310 ref load regulation switching regulator reference and dac output
max1620/max1621 digitally adjustable lcd bias supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.3v, v batt = 10v, t a = 0? to +85? , unless otherwise noted.) timing characteristics ( t a = 0? to +85? , unless otherwise noted.) -20? i dout 0? i sda = -6ma v in = 0v or v in = v dd v dd = 5.5v v dd = 5.5v 3.0v v dd 3.6v 3.0v v dd 3.6v 48.39mv step size v in = 0v or v in = v dd guaranteed monotonic 0? i dout 40? v 0.4 ? ? scl, sda, sus input leakage current v 0.6 scl, sda, sus input low voltage v 2.3 1.4 scl, sda, sus input high voltage ? v 0.6 v 0 0.007 dout minimum output voltage (note 3) 2.3 v 1.4 up, dn, shdn , pol input high voltage lsb dout differential nonlinearity bits 5 dout resolution ? ref - ref + 0.02 0.02 dout maximum output voltage (note 3) v up, dn, shdn , pol input leakage current ? up, dn, shdn , pol input low voltage sda output low voltage conditions units min typ max parameter digital inputs and outputs (note 4) (note 4) (note 4) conditions 1 scl falling edge to sda valid master clocking in data ? t dv ? 4 t hd:sta start condition sda to scl hold time ? 4.7 t su:sta start condition scl to sda setup time ? 4 t high scl high time ? 4.7 t low scl low time ns 300 t f scl/sda fall time ? 1 t 1 pulse width high (up, dn) ? 1 t r scl/sda rise time ns 0 t hd:dat scl to sda data-hold time ns 500 t su : dat sda to scl data-setup time ? 1 t 2 pulse width low (up, dn) ? 1 t 3 pulse separation (up, dn) ? 1 t 4 counter reset time units min typ max symbol parameter ? 4 t su:sto stop condition scl_ to sda_ setup time max1620 (figure 1) max1621 (figures 2 and 3)
max1620/max1621 digitally adjustable lcd bias supplies 4 _______________________________________________________________________________________ operating mode, output in regulation ? 150 250 0? i ref 25? no load ref load regulation voltage on pok rising v pol = v dd , 3.0v v dd 5.5v fb = 0v - 50mv 3.0 5.5 4v batt 12v v dd operating range fb = ref + 100mv pol = agnd, 3.0v v dd 5.5v mv 510 v 1.44 1.5 1.56 ref voltage v 27 positive output voltage 0.957 0.992 1.027 shutdown mode, v shdn = v dd 20 -10 120 fb input current (note 3) v dd supply current v -30 10 mv -10 0 10 v 1.5 2.8 undervoltage lockout threshold (note 1) na 1.44 1.5 1.56 ?-v microsecond-volt time constant (k-factor) 16 24 v 1.8 20 batt operating range (note 2) -27 negative output voltage fb regulation voltage v pok threshold voltage dout maximum output voltage (note 3) v ref - ref + 0.02 0.02 0? i dout 40? -20? i dout 0? dout minimum output voltage (note 3) v 0 0.01 guaranteed monotonic dout differential nonlinearity lsb 1 up, dn, shdn , pol input high voltage 3.0v v dd 3.6v 1.4 v dd = 5.5v 2.3 v up, dn, shdn , pol input low voltage 0.6 v 3.0v v dd 3.6v 1.4 v dd = 5.5v 2.3 scl, sda, sus input low voltage 0.6 v sda output low voltage i sda = -6ma 0.4 v conditions units min typ max parameter electrical characteristics (v dd = 3.3v, v batt = 10v, t a = -40? to +85? . typical values are at t a = +25?, unless otherwise noted. limits over this temperature range are guaranteed by design.) v scl, sda, sus input high voltage v switching regulator reference and output digital inputs and outputs
max1620/max1621 digitally adjustable lcd bias supplies _______________________________________________________________________________________ 5 timing characteristics (v dd = 3.3v, v batt = 10v, t a = -40? to +85? . typical values are at t a = +25?, unless otherwise noted. limits over this temperature range are guaranteed by design.) conditions 4 stop condition scl_ to sda_ setup time ? t su:sto ? 4 t hd:sta start condition sda_ to scl_ hold time ? 4.7 t su:sta start condition scl_ to sda_ setup time ? 4 t high scl high time ? 4.7 t low scl low time ns 300 t f scl/sda fall time ? 1 t 1 pulse width high (up, dn) ? 1 t r scl/sda rise time ns 0 t hd:dat scl_ to sda_ data-hold time ns 500 t su : dat sda_ to scl_ data-setup time ? 1 t 2 pulse width low (up, dn) ? 1 t 3 pulse separation (up, dn) ? 1 t 4 counter reset time units min typ max symbol parameter note 1: the setting in the dac is guaranteed to remain valid as long as v dd is greater than the uvlo threshold. note 2: batt operating range is guaranteed by the microsecond-volt time constant specification. note 3: current sourced from a pin is denoted as positive current. current sunk into a pin is denoted as negative current. note 4: guaranteed by design. __________________________________________typical operating characteristics (v dd = 5v, v batt = 10v, l1 = 100?, t a = +25?, unless otherwise noted.) 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 10203040506070 efficiency vs. output current max1620/21-01 output current (ma) efficiency (%) +25v +15v 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0 10203040506070 efficiency vs. output current max1620/21-02 output current (ma) efficiency (%) -25v -15v 0.70 0.75 0.80 0.85 0.90 0.95 1.00 12 14 16 18 20 22 24 26 efficiency vs. output voltage max1620/21-03 output voltage (v) efficiency (%) +10ma +20ma 1 scl falling time to sda valid master clocking in data ? t dv max1620 (figure 1) max1621 (figures 2 and 3)
max1620/max1621 digitally adjustable lcd bias supplies 6 _______________________________________________________________________________________ _____________________________typical operating characteristics (continued) (v dd = 5v, v batt = 10v, l1 = 100?, t a = +25?, unless otherwise noted.) 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -26 -24 -22 -20 -18 -16 -14 -12 efficiency vs. output voltage max1620/21-04 output voltage (v) efficiency (%) -10ma -20ma 0.70 0.75 0.80 0.85 0.90 0.95 1.00 2 4 6 8 10 12 14 16 18 20 efficiency vs. v batt max1620/21-05 v batt (v) efficiency (%) +20v, +10ma -20v, -10ma 0 20 40 60 80 100 120 140 160 180 200 01 2345 supply current vs. supply voltage max1620/21-06 supply voltage (v) supply current ( m a) 100 125 150 175 200 -40 -20 0 20 40 60 80 supply current vs. temperature max1620/21-07 temperature (?) supply current ( m a) 1.49 1.50 1.51 -40 -20 0 20 40 60 80 reference voltage vs. temperature max1620/21-10 temperature (?) reference voltage (v) 0 2 4 6 8 10 12 14 16 18 20 01 2345 shutdown supply current vs. supply voltage max1620/21-08 supply voltage (v) supply current ( m a) 6 8 10 12 14 16 18 20 -40 -20 0 20 40 60 80 shutdown supply current vs. temperature max1620/21-09 temperature (?) supply current ( m a) 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 2.5 3.0 3.5 4.0 4.5 5.0 k-factor vs. supply voltage max1620/21-11 supply voltage (v) k-factor ( m s-v) 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 -60 -40 -20 0 20 40 60 80 100 k-factor vs. temperature max1620/21-12 temperature (?) k-factor ( m s-v)
max1620/max1621 digitally adjustable lcd bias supplies _______________________________________________________________________________________ 7 15 16 17 18 19 20 21 22 23 24 25 0 5 10 15 20 k-factor vs. v batt max1620/21-13 v batt (v) k-factor ( m s-v) line-transient response v out (ac coupled, 5mv/div) v dd (ac coupled, 1v/div) i load = 20ma 2ms/div 5.3v 3.3v max1620/21-14 load-transient response v out (ac coupled, 20mv/div) i out (10ma/div) 20ma 0 i load = 0ma to 20ma 2ms/div max1620/21-15 _____________________________typical operating characteristics (continued) (v dd = 5v, v batt = 10v l1 = 100?, v out = 22.3v, t a = +25?, unless otherwise noted.)
max1620/max1621 digitally adjustable lcd bias supplies 8 _______________________________________________________________________________________ external transistor drive, high dhi 16 16 external transistor drive, low dlo 15 15 switching-voltage sense input lx 14 14 power ground pgnd 13 13 analog ground agnd 12 12 ic input supply, 3.0v to 5.5v v dd 11 11 dac output voltage logic-level shutdown input (active-low) system management bus suspend-mode input (active-low) power ok voltage-sense input, 1v threshold reference voltage output. bypass ref with 0.1? to agnd. logic-level input. pol selects output voltage polarity: high = positive boost, low = negative boost. logic-level input. a rising edge on up increases ? v out ? . up = dn = high resets the counter to mid-scale. dout system management bus serial-clock input battery voltage-sense input system management bus serial-data input and open-drain output 10 logic-level input. a rising edge on dn decreases ? v out ? . up = dn = high resets the counter to mid-scale. 10 function shdn 4 sus 4 pok 5 5 ref 6 6 pol 7 7 up 2 feedback voltage input fb 9 scl 2 batt 3 3 sda 1 9 open-drain output. lcdon controls lcd with external pnp. lcdon 8 dn 1 8 max1621 max1620 name pin ______________________________________________________________pin description
max1620/max1621 digitally adjustable lcd bias supplies _______________________________________________________________________________________ 9 t 3 t 1 up dn t 2 t 4 t su:sta t su:dat t su:dat t hd:dat t hd:dat t hd:sta scl start condition a5 clocked into slave a4 clocked into slave a3 clocked into slave most significant address bit (a6) clocked into slave sda t low t high t su:sto t dv t dv scl rw bit clocked into slave acknowledged bit clock into master most significant bit clocked slave pulling sda low sda ? ? ? ? figure 1. max1620 up and dn signal timing figure 2. max1621 smb serial-interface timing?ddress figure 3. max1621 smb serial-interface timing?cknowledge
max1620/max1621 digitally adjustable lcd bias supplies 10 ______________________________________________________________________________________ r1 360k 2v to 12v batt pok d1 mbrs0540 n1 mmft3055vl q1 mmbt2907 v dd pol shdn (sus) dn (sda) up (scl) ref agnd 3 5 optional 11 7 4 1 2 6 12 ( ) are for max1621. note: connections to digital inputs not shown. 14 16 15 13 r3 300k r4 300k r5 2.2m c6 100pf 10 9 8 lx dhi dlo pgnd dout fb lcdon 3v to 5.5v c1 0.1 m f c2 0.1 m f r2 100k r8 10k to ref d3 1n6263 (any schottky) c3 22 m f c5 22 m f 12.5v to 23.5v out voutsw optional r6 56k r7 56k l1 100 m h max1620 max1621 u1 _______________detailed description the max1620/max1621 are step-up power controllers that drive an external n-channel fet or npn transistor to convert power from a 1.8v to 20v battery to a higher positive or negative voltage. they are configured as negative-output, inverting power controllers with one additional diode and one additional capacitor. either configuration? output voltage can be adjusted with external resistors, or digitally adjusted with an internal digital-to-analog converter (dac). the max1620 uses pin-defined controls for the dac, while the max1621 communicates with the dac via the smbus interface. operating principle the max1620/max1621 operate in discontinuous- conduction mode (where the inductor current ramps to zero by the end of each switching cycle) and with a constant peak current, without requiring a current- sense resistor. switch on-time is inversely proportional to the input voltage v batt by a microsecond-volt con- stant, or k-factor, of 20?-v (e.g., for v batt = 10v, on-time = 2?). for an ideal boost converter operating in discontinu- ous-conduction mode (no power losses), output current is proportional to input voltage and peak inductor current: i pk is proportional to on-time (t on ), which, for these parts, is determined by the k-factor: i pk = k-factor / l discontinuous conduction is detected by monitoring the lx node voltage. when the inductor? energy is com- pletely delivered, the lx node voltage snaps back to the batt voltage. when this crossing is sensed, anoth- er pulse is issued if the output is still out of regulation. positive output voltage to select a positive output voltage, tie the polarity pin (pol) to v dd and use the typical boost topology shown in figure 4. fb regulation voltage is 1.5v. for optimum stability, v out should be greater than 1.1 (v batt ). negative output voltage to select a negative output voltage, tie pol to gnd (figure 5). in this configuration, the internal error amplifi- er? output is inverted to provide the correct feedback polarity. fb regulation voltage is 0v. d1, d2, c4, and c5 form an inverting charge pump to generate the negative voltage. this allows application of the positive boost switching topology to negative output voltages. the negative output circuit has two possible connec- tions. in the standard connection, d1? cathode is con- nected to batt. this connection features the best output ripple performance, but ? v out ? must be limited to no more than 27v - 1.1(v batt ). if a larger negative voltage is needed, an alternative connection allows a maximum negative output of -27v, but with the addition- al constraint that ? v out ? > 1.1v batt . to use the alter- native circuit, connect d1? cathode to ground rather than batt (figure 6). increase c4 to 2.2 m f to improve output ripple performance. the negative charge pump limits the output current to the charge transferred each cycle multiplied by the i 1 2 i v / v out pk batt out = figure 4. typical operating circuit?ositive output
max1620/max1621 digitally adjustable lcd bias supplies ______________________________________________________________________________________ 11 maximum switching frequency. the following equation represents the output current for the ideal case (no power losses) of figure 5: this means that a higher peak current is required to achieve the same output current in the negative output circuit as in the positive output circuit. the output current for figure 6 uses the same current equation as the positive boost. output voltage control the output voltage is set with a voltage divider to the feedback pin (fb). for a positive output, the divider is referred to gnd; for a negative output, the divider is referred to ref. output voltage can be adjusted with an internal dac summing current into fb through an external resistor. the 5-bit dac is controlled with a user-programmable up/down counter. on power-up or after a reset, the counter sets the dac output to 10000 binary, or half- scale. i x (k - factor / l) x v / (v v ) out batt batt out =+ 1 2 2v to 15v batt pok n1 mmft3055vl v dd pol shdn (sus) dn (sda) up (scl) ref agnd 3 5 11 7 4 1 2 6 12 ( ) are for max1621. note: connections to digital inputs not shown. 14 16 15 13 r3 300k r4 300k r5 1.2m c6 100pf 10 9 8 lx dhi dlo pgnd dout fb lcdon 3v to 5.5v c1 0.1 m f c2 0.1 m f c3 22 m f c5 22 m f -6v to -12v out l1 100 m h d1 mbrs0540 d2 mbrs0540 c4 1 m f max1620 max1621 u1 r8 10k to ref d3 1n6263 (any schottky) 2v to 12v batt pok n1 mmft3055vl v dd pol shdn (sus) dn (sda) up (scl) ref agnd 3 5 11 7 4 1 2 6 12 ( ) are for max1621. note: connections to digital inputs not shown. 14 16 15 13 r3 300k r4 300k r5 2.7m c6 100pf 10 9 8 lx dhi dlo pgnd dout fb lcdon 3v to 5.5v c1 0.1 m f c2 0.1 m f c3 22 m f c5 22 m f -13.5v to -27v out l1 100 m h d2 mbrs0540 d1 mbrs0540 c4 2.2 m f max1620 max1621 u1 r8 10k to ref d3 1n6263 (any schottky) figure 5. typical operating circuit?egative output figure 6. alternative negative output?aximum voltage
max1620/max1621 digitally adjustable lcd bias supplies 12 ______________________________________________________________________________________ the max1620 controls the dac counter with the up and dn pins. a rising edge on up increases ? v out ? by decrementing the counter and decreasing the dac output voltage one step; a rising edge on dn de- creases ? v out ? by incrementing the counter and increasing the dac output voltage one step. holding both up and dn high resets the counter to half-scale. the counter will not roll over at either the fs or zero code. the control direction of up and dn reverses for a negative output, to maintain the same control direction of the output voltage in absolute magnitude. the max1621 controls the counter to the dac through the smbus interface. the counter is treated as a 5-bit register and resets on power-up. the setting in the dac is guaranteed to remain valid as long as v dd is greater than the uvlo threshold (see note 1 in the electrical characteristics ). the max1620/max1621? open-drain dmosfet ( lcdon ) can be used to disconnect the lcd panel from the positive bias voltage with an external transistor. the fet turns off ( lcdon = float) if power-ok voltage (pok) falls below 1v. in the max1621, lcdon can also be controlled by the smb command. lcdon cannot switch negative output voltages. to prevent uncontrolled boosting when the output is disconnected, the feedback resistors must sense the boosted voltage rather than the output of the lcdon switch (figure 4). shutdown mode the max1620 shuts down when the shdn pin is low. the internal reference and biasing circuitry turn off, and the supply current drops to 9 m a. in shutdown, dout = 0v and lcdon floats. up/dn are ignored to preserve the dac state for the max1620. tie unused logic inputs to agnd for lowest operating current. the max1621 can be shut down using the smbus interface (table 2). reset modes if the max1620 is not in shutdown mode, the dac can be reset to mid-scale by holding up and dn high. mid- scale is 16 steps from the minimum dac output and 15 steps from the maximum. the max1620/max1621 reset the dac counter to mid- scale at power-up or when v dd is below the undervolt- age lockout threshold of 2.2v (typ). max1621 digital interface a single byte of data written over the intel smbus con- trols the max1621. figures 7 and 8 show example single-byte writes. the max1621 contains two 2-bit reg- isters for storing configuration data, and one register for the 5-bit dac data. tables 1 and 2 describe the data format for the configuration registers. the max1621 responds only to its own address (0101100 binary). the regsel bit addresses the configuration registers. regsel = 0 for the sus register; regsel = 1 for the opr register. each configuration register consists of a shdn bit and an lcdon bit. one of the two configura- tion registers is always active. the state of the sus pin determines the active register. the opr register is active with sus = high. the sus register is active with sus = low. each byte written to the max1621 updates the dac reg- ister. dac data is preserved in shutdown and when tog- gling between configuration registers. since there is only one dac register, sus cannot be used to toggle between two dac codes. status information can be read from the max1621 using the smbus read-byte protocol. figure 9 shows an exam- ple status read and table 3 describes the status- information format. during shutdown (sus = 1 and opr-shdn = 0, or sus = 0 and sus-shdn = 0), the max1621 serial inter- face remains fully functional and can be used to set either the opr-shdn or sus-shdn bits to return the max1621 to its normal operational state. separate/same power for l1 and v dd separate voltage sources can supply the inductor (l1) and the ic (v dd ). this allows operation from low-voltage batteries as well as high-voltage sources because chip bias (150?) is provided by a logic supply (3v to 5.5v) while output power is sourced directly from the battery to l1. conversely, l1 and v dd can also be supplied from one supply if it remains with v dd ? operating limits (3v to 5.5v). if l1 and v dd are fed from the same volt- age, d3 and r8 (figures 4, 5, 6, and 10) can be omit- ted, and batt may be connected directly to v dd .
max1620/max1621 digitally adjustable lcd bias supplies ______________________________________________________________________________________ 13 reserved for future use. dac register data reserved for future use. if the voltage applied to pok is greater than 0.992v and the max1621 is not shut down, this bit returns 1; otherwise, it returns 0. description 5 d4 (msb) d3 d2 d1 d0 4 3 2 1 0 6 pok 7 name bit with sus = high, 1 = lcd on, and 0 = lcd off. dac input data with sus = high, 1 = operating, and 0 = shutdown. register select. a one in this bit writes the next two bits into the opr register and the remaining five bits into the dac register (figure 7). description 1 opr-lcdon 5 1 0 0 0 0 d4 (msb) d3 d2 d1 d0 4 3 2 1 0 1 opr- shdn 6 regsel 7 name por state* bit table 2. max1621 configuration byte with regsel = 1 (write to opr register) * initial register state after power-up. table 3. max1621 status bits with sus = low, 1 = lcd on, and 0 = lcd off. dac input data with sus = low, 1 = operating, and 0 = shutdown. register select. a zero in this bit writes the next two bits into the sus register and the remaining five bits into the dac register (figure 7). description 0 sus -lcdon 5 1 0 0 0 0 d4 (msb) d3 d2 d1 d0 4 3 2 1 0 0 sus - shdn 6 regsel 7 por state* bit name * initial register state after power-up. table 1. max1621 configuration byte with regsel = 0 (write to sus register)
start condition most significant address bit least significant address bit slave pulls sda low slave pulls sda low regsel d4 opr-lcdon opr-shdn d3 d2 d1 d0 slave acknowledge slave acknowledge most significant data bit least significant data bit scl sda r/w bit dac data figure 8. max1621 serial-interface single-byte write example (regsel = 1) max1620/max1621 digitally adjustable lcd bias supplies 14 ______________________________________________________________________________________ start condition most significant address bit least significant address bit slave pulls sda low slave pulls sda low regsel d4 sus-shdn dac data d3 d2 d1 d0 slave acknowledge slave acknowledge most significant data bit least significant data bit scl sda r/w bit sus-lcdon figure 7. max1621 serial-interface single-byte write example (regsel = 0)
max1620/max1621 digitally adjustable lcd bias supplies ______________________________________________________________________________________ 15 start condition most significant address bit least significant address bit slave pulls sda low max1621 drives sda d4 pok d3 d2 d1 d0 slave acknowledge most significant data bit scl sda r/w bit figure 9. max1621 serial-interface read example design procedure __________and component selection the max1620/max1621 output voltage can be adjusted manually or via a digital interface. in addition, positive bias voltage can be switched with lcdon using an external pfet or pnp transistor. output adjustment setting the minimum output voltage the minimum output voltage is set with a resistor-divider (r4-r5, figure 4) from v out to agnd. the fb threshold voltage is 1.5v. choose r4 to be 300k so that the cur- rent in the divider is about 5?. determine r5 as follows: r5 = r4 x (v out,min - v fb ) / v fb for example, if v out,min = 12.5v: r5 = 300k x (12.5 - 1.5) / (1.5) = 2.2m mount r4 and r5 close to the fb pin to minimize para- sitic capacitance. for a negative output voltage, the fb threshold voltage is 0v, and r4 is placed between fb and ref (figures 5 and 6). again, choose r4 to be 300k so that the cur- rent in the divider is about 5a. then determine r5 as follows: r5 = r4 x ? v out,min / v ref ? for example, if v out,min = -12.5v: r5 = 300k x ? (12.5) / (1.5) ? = 2.5m
max1620/max1621 digitally adjustable lcd bias supplies 16 ______________________________________________________________________________________ setting the maximum output voltage (dac adjustment) the dac is adjustable from 0v to 1.5v in 32 steps, and 1lsb = 1.5v / 31. dac adjustment of v out is provided by adding r3 to the divider circuit (figure 4). be sure that v out,max does not exceed the lcd panel rating. for v out,max = 25v and v out,min = 12.5v, r3 is deter- mined as follows: r3 = r5 x (v fb ) / (v out,max - v out,min ) = 2.2m x (1.5) / (25 - 12.5) = 264k the general form for v out as a function of the dac out- put (v dout ) is: v out = v out,min + (v fb - v dout ) x r5 / r3 at power-up the dac resets to mid-scale (10000), which corresponds to v dout = 0.774v; therefore, the output voltage after reset is as follows: v out,reset = v out,min + (1.5 - 0.774) x r5 / r3 note that for a positive output voltage, v out increases as v dout decreases. v out,max corresponds to v dout = 0v, and v out,min corresponds to v dout = 1.5v. for a negative output voltage, v out = v out,min + (v fb - v dout ) x r5 / r3. assume v out,max = -25v and v out,min = -12.5v; then determine r3 and v out,reset as follows: r3 = r5 x (v fb - v dout,max ) / (v out,max - v out,min ) = 2.5m x (0 - 1.5) / (-25 - -12.5) = 300k v out,reset = -12.5 + (0 - 0.774) x (2.5m) / (300k) = -18.95v note that for a negative output voltage, ? v out ? increases as v dout increases. ? v out,max ? corresponds to v dout = 1.5v, and ? v out,min ? corresponds to v dout = 0v. potentiometer adjustment the output can be adjusted with a potentiometer instead of the dac. choose r pot = 100k , and connect it between ref and gnd. connect r3 to the potentiome- ter? wiper, instead of to dout. the same design equa- tions as above apply. controlling the lcd using pok and lcdon when voltage at pok is greater than 1v, the open-drain lcdon output pulls low. lcdon withstands 27v; there- fore, it can drive a pfet or pnp transistor to switch on the max1620/max1621? positive output. the following represent three cases for using this feature: 1) as an off switch, to ensure that a positive boosted output goes to 0v during shutdown. in this case, connect pok to shdn . without this switch, the posi- tive output falls to one diode-drop below the input voltage (v batt ) in shutdown. lcdon is not needed for negative outputs, which will fall to 0v in shut- down anyway. 2) as an output sensing cutoff for positive outputs. connect pok to the feedback voltage divider to sense the output voltage. the output is switched on only when it reaches a set percentage of the set voltage. 3) as an input sensing output cutoff for positive out- puts. connect pok to a voltage divider to sense the input voltage. the output is switched on only when the input reaches the set level (figure 4). to control the open-drain output lcdon by sensing the input voltage, connect a resistor-divider (r1-r2, figure 4) from v batt to pok. choose r2 = 100k. for example, if the minimum battery voltage is 5.3v, deter- mine r1 as follows: r1 = r2 x [(v batt / v pok ) - 1] = 100k x [(5.3 / 0.992) - 1] = 434k lcdon can also be controlled via software (max1621, table 4). table 4. max1621 lcdon output truth table pok pin lcdon output lcdon bit <1v 0 floating <1v 1 floating >1v 1 on, pulls low >1v 0 floating
max1620/max1621 digitally adjustable lcd bias supplies ______________________________________________________________________________________ 17 company part coilcraft (847) 639-6400 do1608 comments size in mm (h x w x l) ? range cd43 up to 68? 3.2 x 4 diameter up to 1mh 3.18 x 4.45 x 6.6 cd54 up to 220? 4.5 x 5.2 diameter sumida usa (847) 956-0666 japan 81-3-3607-5111 cdrh62b up to 330? tdk (847) 390-4373 dt1608 up to 400? 3.18 x 4.45 x 6.6 shielded 3 x 6.2 x 6.2 shielded nlc565050 up to 1mh 5 x 5 x 5.6 tpf0410 up to 1mh 4 diameter x 10 l leaded coil table 6. inductor list lcdon typically drives an external pnp transistor, switching a positive v out to the lcd. r7 limits the base current in the pnp; r6 turns off the pnp when lcdon is floating. r6 and r7 can be the same value. choose r7 such that the minimum base current is greater than 1/50 of the collector current. for example, assume v out,min = 12.5v and i lcd = 10ma, then determine r7 as follows: r7 50 x (12.5 - 0.7) / 10ma = 59k remember that lcd voltage is the regulated output volt- age minus the drop across the pnp switch. the drop across the external transistor (typically 300mv) must be accounted for. if a pfet is preferred for the lcdon switch, r6 and r7 in figure 4 may both be raised to 1m or more to reduce operating current. be sure to choose a p fet with ade- quate breakdown voltage. since load current is typically on the order of 10ma, an on-resistance of 10 or less is usually adequate. choosing an inductor practical inductor values range from 33? to 1mh; however, 100? is a good choice for a wide range of applications. inductors with a ferrite core or equivalent are recommended. the inductor? current rating should exceed the peak current as set by the k-factor and the coil inductance; however, for most inductor types, the coil? specified current can be exceeded by 20% with no impact on efficiency. the peak current is set by the coil inductance as follows: i pk = k-factor / l and if we assume that v batt,min = 5.3v, v out,max = 25v, i out,min = 15ma, and a minimum k-factor of 16?-v, then the required i pk is: i pk = 2 x 15ma x 25 / 5.3 = 142ma and l = 16?-v / 142ma = 113? the next-lowest practical inductor value is 100?. its current rating must be: 24?-v (maximum k-factor) / 100? = 240ma table 5 summarizes the minimum inductance value needed to provide various output currents at several minimum input voltages. table 6 lists some suitable coil types and manufacturers, but is not intended to be a complete list. i 1 2 i v / v out,min pk batt,min out,max = 1.8v 2.7v 3.6v 5.4v 7.2v 12v iout 5ma 100? 150? 220? 330? 390? 680? 10ma 56? 82? 100? 150? 220? 330? 20ma 27? 39? 56? 82? 100? 180? 30ma 18? 27? 33? 56? 68? 120? v batt,min table 5. maximum inductance vs. i out and v batt,min (20v output)
max1620/max1621 digitally adjustable lcd bias supplies 18 ______________________________________________________________________________________ diode selection the high maximum switching frequency of 300khz requires a high-speed rectifier. schottky diodes, such as the mbrs0540, are recommended. to maintain high effi- ciency, the average current rating of the schottky diode must be greater than the peak switching current. choose a reverse breakdown voltage greater than the positive output voltage or greater than the negative output volt- age plus v batt . external switching transistor again, the high maximum switching frequency requires a high-speed switching transistor to maintain efficiency. logic-level n-channel mosfets, such as the mmft3055vl, are recommended (n1). choose a v ds rating greater than the positive output voltage or greater than the negative output voltage plus v batt . to save cost in certain applications, a bipolar transistor may be substituted for the mosfet with a decrease in efficiency. the conditions favoring substitution are limit- ed input voltage range (v dd ), low maximum battery voltage (v batt ), and low output current. for example, v dd = 3.0v to 3.6v, v batt,max = 12v, and i out = 5ma favors a bipolar transistor substitution to reduce cost. to modify the typical operating circuit (figures 4 and 5) for a bipolar switching transistor, connect the collec- tor to the inductor, the base to dlo, and the emitter to pgnd (figure 10). connect the base to dhi through a series resistor to limit the base current. choose the resistor such that the minimum base current is greater than 1/20 of the peak inductor current. for example, assume v dd,min = 3v and i pk = 100ma; then r s 20 x (3 - 0.7) / 100ma = 460 . output filter capacitor a 22?, 35v, low-esr, surface-mount tantalum output capacitor is sufficient for most applications. output rip- ple voltage is dominated by the peak switch current multiplied by the output capacitor? effective series resistance (esr). 100mvp-p output ripple is a good tar- get for the trade-off between cost and performance. capacitors smaller than 22? may be used for light loads and lower peak current. surface-mount capaci- tors are generally preferred because they lack the inductance and resistance of their through-hole equiva- lents. the avx tps series and the sprague 593d and 595d series are good choices for low-esr surface- mount tantalum capacitors. moderate-performance aluminum-electrolytic or tanta- lum capacitors can be successfully substituted in cost- sensitive applications with low output current. matsuo and nichicon provide suitable choices. input bypass capacitor two inputs, v dd and v batt , require bypass capacitors. bypass v dd with a 0.1? ceramic capacitor as close to the ic as possible. the battery supplies high currents to the inductor and requires local bulk bypassing close to the inductor. a 22? low-esr surface-mount capaci- tor is sufficient for most applications. smaller capaci- tors are acceptable if peak inductor current is low or the battery? internal impedance is low and the battery is close to the inductor. charge-pump capacitor (negative output) possible negative output topologies are shown in figures 5 and 6. overall efficiency for the negative out- put configuration is less than for the positive output circuit because of the extra components in the power- transfer path. for efficient charge transfer, c4 must have low esr and should be smaller than the output capacitor (c5). c4 sees the same voltage as c5, and should have the same voltage rating. a 1f ceramic capacitor is a practical choice for cost and performance considerations. 2.2? is suggested for figure 6? circuit. feedback-compensation capacitor the high value of the feedback resistors (r3, r4, r5, figure 4) makes the feedback loop susceptible to phase lag because of the parasitic capacitance at the fb pin. to compensate for this, connect a capacitor (c6, figure 4) in parallel with r5. the value of c6 depends on the parallel combination of r3, r4, r5, and the individual circuit layout. typical values range from 33pf to 220pf. reference-compensation capacitor the internal reference uses an external capacitor for frequency compensation. connect a ceramic capacitor with a 0.1? minimum value between ref and ground. pc board layout and grounding due to high current levels and fast switching wave- forms, proper pc board layout is essential. in particu- lar, keep all traces short, especially those connected to the fb pin and those connecting n1, l1, d1, d2, c4, and c5. place r3, r4, and r5 as close to the feedback pin as possible. use a star ground configuration: connect the grounds of the input bypass capacitor, the output capacitor, and the switching transistor together, close to the ic? pgnd pin. tie agnd and pgnd together at the chip.
max1620/max1621 digitally adjustable lcd bias supplies ______________________________________________________________________________________ 19 ___________________chip information transistor count: 341 substrate connected to agnd r1 360k 2v to 12v batt pok d1 mbrs0540+ q1 mmbt4401lt1 q1 mmbt2907 v dd pol shdn (sus) dn (sda) up (scl) ref agnd 3 5 11 7 4 1 2 6 12 ( ) are for max1621. note: connections to digital inputs not shown. 14 16 15 13 r3 300k rs 470 w r4 300k r5 2.2m c6 100pf 10 9 8 lx dhi dlo pgnd dout fb lcdon 3v to 5.5v c1 0.1 m f c2 0.1 m f r2 100k c3 10 m f c5 10 m f 12.5v to 23.5v out voutsw optional r6 150k r7 150k l1 220 m h max1620 max1621 u1 r8 10k to ref d3 1n6263 (any schottky) figure 10. positive output with bipolar switching transistor ___________________________________________________simplified block diagram bias shdn v dd agnd dn (sda) up (scl) shdn (sus) pol ref fb batt pok ( ) are for max1621 only. dout lx dhi dlo pgnd lcdon digital interface bandgap reference 5-bit dac 1.0v 1.5v on-time control max1620 max1621
max1620/max1621 digitally adjustable lcd bias supplies 20 ______________________________________________________________________________________ ________________________________________________________package information qsop.eps

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